Sequential Circuit
Q31.
Consider the partial implementation of a 2-bit counter using T flip-flops following the sequence 0-2-3- 1-0, as shown below. To complete the circuit, the input X should beQ32.
You are given a free running clock with a duty cycle of 50% and a digital waveform f which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip flops) will delay the phase of f by 180^{\circ} ?Q33.
The following arrangement of master-slave flip flops has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively),Q34.
Consider the circuit in the diagram. The \oplus operator represents Ex-OR. The D flip-flops are initialized to zeroes (cleared). The following data : 100110000 is supplied to the "data" terminal in nine clock cycles. After that the values of q_{2}q_{1}q_{0} areQ36.
In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result inQ37.
Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: Advantage of synchronous sequential circuits over asynchronous ones is:Q38.
Consider the circuit given below the initial state Q_{0}=1, Q_{1}=Q_{2}=0. The state of the circuit is given by the value 4Q_{2}+2Q_{1}+Q_{0} Which one of the following is the correct state sequence of the circuit ?Q39.
A 1-input, 2-output synchronous sequential circuit behaves as follows. Let z_{k},n_{k} denote the number of 0's and 1's respectively in initial k bits of the input ( z_{k}+n_{k}=k ). The circuit outputs 00 until one of the following conditions holds. 1. z_{k}-n_{k}=2. In this case, the output at the k -th and all subsequency clock ticks is 10. 2. n_{k}-z_{k}=2. In this case, the output at the k -th and all subsequent clock ticks is 01. What in the minimum number of states required in the state transition graph of the above circuit?Q40.
What is the final value stored in the linear feedback shift register if the input is 101101?